1) Field of the Invention
The present invention relates to a metal oxide semiconductor (MOS) transistor in which a gain coefficient of a field-effect transistor can be modulated. The invention particularly relates to the MOS transistor to be a basic device which realizes new-type LSI devices such as self-optimizing LSI and a self-adapting LSI in which high performance of LSI is realized by optimizing individual transistors after manufacturing LSI in a large-scale and highly integrated semiconductor integrated circuit (LSI) device in the future.
2) Description of the Related Art
Recent LSI devices are large scaled and highly integrated according to development of miniaturized devices, and a system-on-chip is realized. As a result, it is being required to integrate a large variety of functional circuits in chips. In the design of such large-scale LSI devices, it is particularly important to optimize operation timing or the like between the functional circuits in order to properly operate the many integrated functional circuits.
On the other hand, the performance of LSI device has been improved mainly by miniaturization of devices for 30 or more years since its invention. In these days where various physical limits become obvious in the miniaturization of devices, however, it becomes extremely difficult to manufacture integrated circuit devices stably and uniformly.
As a result, the design of the LSI devices requires measures that secures an operating margin in order to cover a process fluctuation which cannot be avoided in the manufacturing process of LSIs. The measures that secures the operating margin interferes with heightening of performance of the large-scale LSI devices according to diversification and enlargement of the devices.
In such future LSI devices, non-uniformity of device characteristics for each LSI chip,.such as dispersion (distribution) of intra-chip device characteristics and a median fluctuation (shift) of device characteristics due to process fluctuation, and difficulty of LSI physical design (performance optimization design) due to the non-uniformity become obvious. For this reason, a performance heightening method for LSI devices which depends only on the miniaturization of devices is reaching a limit.
In order to improve the high performance of LSI devices, it is indispensable to establish new LSI design and manufacturing method in which the dispersion of the device characteristics larger than a certain level is premised. As one method relating to the LSI design and manufacturing method in which the dispersion of the device characteristics larger than a certain level is premised, a method of providing a self-adjusting function into LSI chips is considered.
Specifically, in such a method, electrical characteristics adjustment based on setting of a size (a gate length and a gate width) in individual field-effect transistors (e.g. MOS transistors), which is conventionally performed at the final LSI design step (physical design), is designed to be performed automatically by each chip itself after manufacturing of LSIs. As a result, the electrical characteristics of individual MOS transistors in the LSI chips are optimized so that the chip performance is heightened.
In order that the LSI chips realize the self-adjustment performance, it is necessary to provide a design that a program or electrical dynamics can automatically adjust the electrical characteristics into LSI chips. In order to realize this design, therefore, at least some kind of means that electrically modulates the electrical characteristics is essential, and technical development of such means gives the key to realize the self-adjustment function.
The method of electrically modulating the electrical characteristics which can be realized by using a conventional art is explained below. In the conventional art, when the electrical characteristics are electrically modulated, a method using a circuit configuration and a method of modulating characteristics of devices are mainly adopted.
The method using the circuit configuration includes a method of establishing a circuit configuration such that a plurality of MOS transistors are used and a number of their parallel connection is switched by an electric switch as explained in CIRCUIT 1 to CIRCUIT 4, for example. According to this method, effective electrical characteristics (gain coefficient) when the entire circuit is regarded as one MOS transistor can be modulated. The method that realizes the circuit is, however, very inefficient from viewpoints of adjustment accuracy and a circuit scale as explained below.
A configuration (CIRCUIT 1) such that two MOS transistors are connected in parallel is considered. In CIRCUIT 1, a normal signal voltage is applied to a gate electrode of one MOS transistor, and a signal voltage and an OFF voltage for OFF operation are switched so as to be applied to a gate electrode of the other MOS transistor.
According to this CIRCUIT 1, when a switch connects the signal voltage with the gate electrode of the other MOS transistor, the two MOS transistors connected in parallel-serve as one MOS transistor in this circuit. Further, when the switch connects the OFF voltage with the gate electrode of the other MOS transistor, only one MOS transistor functions in this circuit. As a result, the substantial gain coefficient of the MOS transistor can be modulated.
A configuration (CIRCUIT 2) such that five MOS transistors are connected in parallel is considered. In CIRCUIT 2, a normal signal voltage is applied to a gate electrode of one MOS transistor, and a signal voltage and an OFF voltage for OFF operation are switched so as to be applied to gate electrodes of the other four MOS transistors.
According to this CIRCUIT 2, sixteen variations can be realized by states of four switches. That is to say, the gain coefficients of the four MOS transistors are set to be a multiple of a power of 2, so that coefficients of 16 degrees can be set with equal intervals.
A configuration (CIRCUIT 3) such that two MOS transistors are connected in series is considered. In CIRCUIT 3, a normal signal voltage is applied to a gate electrode of one MOS transistor, and a signal voltage and an ON voltage for ON operation are switched so as to be applied to a gate electrode of the other MOS transistor.
According to this CIRCUIT 3, when a switch connects the signal voltage with the gate electrode of the other MOS transistor, the two MOS transistors are connected in series and perform the same operation. For this reason, the two MOS transistors serve as one normal MOS transistor in this circuit. Further, when the switch connects the ON voltage with the gate electrode of the other MOS transistor, this circuit serves as a circuit in which the one MOS transistor is connected with ON resistance of the other MOS transistor in series.
A configuration (CIRCUIT 4) such that two MOS transistors are connected in series is considered. In CIRCUIT 4, a normal signal voltage is applied to a gate electrode of one MOS transistor, and a control voltage which changes the ON resistance is applied to the gate electrode of the other MOS transistor. This circuit serves as a circuit that adjusts the resistance connected with the one MOS transistor in series.
The switch normally includes a complementary MOS (CMOS) switch which is connected with a P-channel MOS (hereinafter, “PMOS”) transistor and an N-channel MOS (hereinafter, “NMOS”) transistor in parallel, an inverter which generates a gate signal of the CMOS switch, and a latch circuit which holds a state of the switch. Totally about 24 MOS transistors are necessary.
In the circuit configuration examples adopting the series connection in CIRCUIT 1 and CIRCUIT 2, therefore, a trade-off relationship is established between accuracy of the characteristics adjustment and circuit scale, and this causes a problem that the circuit scale becomes large when the adjustment accuracy is heightened.
Further, in the circuit configuration examples adopting the parallel connection in CIRCUIT 3 and CIRCUIT 4, the circuit scale becomes large, and a resistance component which causes nonlinear characteristics of an input signal intervenes in series. For this reason, an effective characteristics adjustment range is limited.
The circuit configurations that modulate the electrical characteristics of the transistor has essential restriction such that devices whose number is several times or several-dozen times a number of devices to be adjusted should be required. These configurations hardly fit in packaging of the self-adjustment function which promotes high integration and heightens the performance of the LSI devices.
In prior MOS transistors, it is not easy to change the electrical characteristics after manufacturing LSI, but electrical characteristics of devices can be modulated by controlling a back gate voltage. The electrical characteristics of MOS transistors are roughly explained.
The electrical characteristics of MOS transistors can be expressed by the following equations in which Ids is a source-drain current, Vds is a source-drain voltage, Vgs is a gate voltage, Vt is a threshold voltage, and β is a gain coefficient. The equations (1) and (2) below represent that no short channel effect or the like for simplicity is not produced.Vds>Vgs−Vt, Ids≈β(Vgs−Vt)2/2   (1)Vds≦Vgs−Vt, Ids≈β((Vgs−Vt)Vds−Vds2/2)   (2)
The gain coefficient β can be expressed by the following equation (3) in which W is a gate width, L is a gate length, Tox is a thickness of a gate insulating film, μ is a carrier mobility, and ε is permittivity of the gate insulating film.β≈μεW/(L·Tox)  (3)
As understood from the equations (1) and (2), the electrical characteristics of MOS transistors depend on the threshold voltage Vt. After LSI is manufactured, the threshold voltage Vt can be changed by controlling a back gate voltage. In a method of changing the electrical characteristics of MOS transistor after the manufacturing of LSI using the conventional art, therefore, the back gate voltage is changed so that the threshold voltage Vt is modulated.
A reverse bias relationship should be, however, maintained between the back gate voltage and the source-drain voltage, and additionally the back gate voltages should be electrically separated from each other for each device to be modulated. For this reason, this method is inadequate to high integration.
Further, a change in the threshold voltage Vt cannot influence the source-drain current Ids only according to a difference between the threshold voltage Vt and the gate voltage Vgs. For this reason, it is difficult that the electrical characteristics of MOS transistors are modulated dynamically only by changing the threshold voltage Vt.
That is to say, the system that modulates the transistor electrical characteristics by changing the threshold value Vt using the conventional art hardly fits in the packaging of the self-adjustment function which promotes high integration and heightens the performance of the LSI devices. This is because of inhibition of an integration degree and fragility of a modulation degree due to the separation of back gate.
In the conventional art, it is not easy to provide the self-adjustment function in a highly integrated manner, or to change the electrical characteristics after the manufacturing of LSI. It is, therefore, desired to develop new devices that can modulate the electrical characteristics dynamically without inhibiting high integration.
In the equation (3), since the carrier mobility μ, the permittivity ε, and the thickness of the gate insulating film Tox are, generally constant, the gain coefficient β can be set by a ratio of the gate width W to the gate length L. The electrical characteristics of MbS transistors which can be set in the physical design of LSI devices are, therefore, the gain coefficient β.
When the gain coefficient β can be modulated, as is clear from the equations, the source-drain current Ids can be strongly influenced in proportion to the product of the gate voltage Vgs and the gain coefficient β. For this reason, the electrical characteristics of MOS transistors can be modulated dynamically. That is to say, the gain coefficient β can be electrically modulated to be about several times or several dozen times, so that correction of dispersion of the device characteristics, automatic compensation of a load change, and the like which match the modulation can be made after the manufacturing of LSI devices.
At this time, it is important for basic devices for active LSI to be capable of analog-modulating the gain coefficient β with a compact device size which does not inhibit high integration.
From such a viewpoint, the inventor has devised a semiconductor device which is capable of modulating a gain coefficient of a field-effect transistor (see Japanese Patent Application Laid-Open No. 2002-222944). The semiconductor device in Japanese Patent Application Laid-Open No. 2002-222944 is called as a gain coefficient variable MOS transistor, and its summary is explained.
Configurational characteristics of the gain coefficient variable MOS transistor are such that a control gate is additionally arranged in a gate area (main gate) in a prior MOS transistor in a slanted manner. That is to say, the gain coefficient variable MOS transistor is characterized in that a triangular area is formed on a source area side and a drain area side which are not overlapped with the main gate in a channel area under a control gate, and these areas form a parallelogram in a state that they sandwiching the main gate.
The modulation characteristics of the gain coefficient β can be set by device shape parameters (a gate width W and a gate length L of the main gate, and an angle θ formed between the main gate and the control gate).
According to this configuration, a direction of an electric field with respect to the gate channel can be controlled by a voltage of the control gate. That is to say, the voltage of the control gate is adjusted, and a conductance of the control gate channel is changed with respect to a conductance of the main gate, so that the effective gate length L and gate width W can be analog-modulated. As a result, the gain coefficient β can be analog-modulated.
The gain coefficient variable MOS transistor is incorporated into LSI, therefore, so that characteristics of a device can be adjusted dynamically by on-chip itself. As a result, a mechanism, that automatically corrects an operation timing between built-in functional circuits due to enlargement of LSI and dispersion of the device characteristics which increases due to miniaturization of devices, can be realized in a highly integrated manner.
In the semiconductor device in Japanese Patent-Application Laid-Open No. 2002-222944, however, since the control gate is arranged so as to be overlapped with the main gate, it is necessary to additionally provide the second gate layer which can be electrically separated from the main gate. As a result, a number of the manufacturing steps of LSI mounted with the semiconductor device increases in comparison with the normal CMOS process, and thus a manufacturing cost increases.
Further, in the semiconductor device in Japanese Patent Application Laid-Open No. 2002-222944, the control gate which forms a certain angle with respect to the main gate is additionally provided in order to form the rectangular area on the main gate on the source area side and the drain area side. For this reason, the size of the device becomes large.
Further, the modulation characteristics of the gain coefficient in the semiconductor device are determined by a conductance ratio of the main gate to the control gate. For this reason, as the conductance of the main gate becomes smaller, the modulation degree of the gain coefficient becomes smaller.